1. Field of the Invention
The invention relates in general to a three-dimensional (3D) semiconductor structure and method of fabricating the same, and more particularly to the three-dimensional resistive random-access memory (RRAM) structure and method of fabricating the same.
2. Description of the Related Art
Integrated circuits are used to control the functions of many modern electronic devices. Memory devices used for storing (write) and retrieving (read) data possess advantages that are easily accessible by the integrated circuits. Various types of memory devices for data storage are known in the art. Generally, memory devices are distinguished by their speed and data retention characteristic.
Memory device falls mainly into two classes: random access memory (“RAM”) and read-only memory (“ROM”). Many improvements and variations of RAMs and ROMs have been advanced to further their performance, and both types of memory have their own advantages and disadvantages. Typically, RAM (i.e. volatile) has fast data transfer rates and efficient writing architectures, but requires continuously power to keep the data. ROM retains the contents even in the absence of power, but is limited in the speed, the number of times to which it may be written, and the manner in which it may be written. ROM mostly comprises Flash memory, EPROM, OTP, EEPROM, and PROM. RAM mostly comprises static RAM (SRAM), dynamic RAM (DRAM).
Static random access memory (SRAM), with very fast access times, retains a value as long as power is supplied. However, its volatility (i.e. it will lose its contents when the power is switched off), large size and stand-by current limit the total size and applications of the memory. DRAM has the smallest cell size, but necessitates a complex refresh algorithm, and is also necessary to supply voltage at all times or the information will disappear (i.e. volatile). Flash memory (i.e. non-volatile memory) is slower to program, and in some cases must erase a large block of memory before being reprogrammed.
Resistive random access memory (RRAM) is a new non-volatile memory type being developed by many companies for a period of time. Different forms of RRAM have been disclosed, based on different dielectric materials, spanning from perovskites to transition metal oxides to chalcogenides. Literature data are giving more indications that RRAM is closest to becoming a universal memory. For, example, RRAM operates at a faster timescale (switching time can be less than 10 ns), and has a simpler smaller cell structure (a 4-8 F2 MIM stack). Compared to flash memory, a lower voltage is sufficient. Compared to DRAM, the data is retained longer (10 years).
Memory devices can be constructed into two-dimensional (2D) cell array or three-dimensional (3D) memory array, wherein the 2D memory cells are matrixed in the X-Y plane. The 3D memory device includes a plurality of stacked memory cells to form a three-dimensional memory array. The three-dimensional memory device is most efficient when the number of cell on each bit line and word line is large. FIG. 1 depicts a cross-sectional view of one conventional three-dimensional (3D) memory device. As shown in FIG. 1, the 3D memory device 1 has two stacked memory cell arrays 10A and 10B. Nevertheless, the 3D memory device may have any number of stacked memory cell arrays. Although each stacked memory cell array of FIG. 1 includes two memory cell units, it could have more for meet the requirement of high density of memory cells. Therefore, the 3D memory device density could be increased in the vertical direction (i.e. z-direction) and also along the x-y plane.
As shown in FIG. 1, the stacked memory cell array 10B is supported by a base layer 11 made of insulation material, such as oxide, nitride, silicon dioxide, or other like insulation materials. The base layer 11 could be formed on a substrate (not shown), in which the base layer 11 and the substrate would support the stacked memory cell arrays 10A and 10B. Each memory cell array includes the plugs formed on the first conductive line (ex. word line) 12 and the plugs are spaced apart by a first insulation layer 16. Each plug includes a metal layer 13 and a metal oxide layer 14. The metal oxide layer 14 acts as a memory element while the cell is programming and erasing. The second conductive lines (ex. bit lines) 18 are formed on the metal oxide layer 14, and the y-direction second conductive lines (ex. bit lines) 18 are orthogonal to a top layer of the x-direction first conductive line (ex. word line) 12. Also, a second insulation layer 19 is formed on the second conductive lines 18. The stacked memory cell arrays 10A and 10B are separated from each other by the second insulation layer 19. During device operation, the conventional memory cell arrays 10A and 10B, which have identical structures, function as two independent units. For example, the programming of the cell of stacked memory cell arrays 10B can be achieved by applying voltages on the first conductive line (ex. word line) 12 and second conductive lines (ex. bit lines) 18. The resistance of the metal oxide layer 14 would be changed by applying different levels of voltage, and variable resistance of the metal oxide layer 14 define different logic states of memory cell. Similarly, the programming of the cell of stacked memory cell arrays 10A, which is independent from the memory cell arrays 10B, can be achieved by applying voltages on the first conductive line 12′ and the second conductive lines 18′.
Although various structures of 3D memory devices have been developed, each stacked memory array of a conventional 3D memory device is programmed by applying voltages on its own word lines and bit lines. Thus, the stacked memory arrays of the conventional 3D memory device are programmed individually. Despite various 3D memory devices have been investigated and known in worldwide memory technologies, it is still desirable to fabricate a high density 3D memory device with more components packed onto each chip for meeting the future needs of smaller electronic product.